Jun

30

Highlights of VLSI Symposium 2008

Filed Under Process Technology, Video Gallery | 1 Comment

I have captured some of the highlights of 2008 Symposium on VLSI Technology here:

  • Continuously driving incremental performance improvement in planar CMOS transistor performance is always one of the themes in VLSI Technology Symposium. This year, a number of companies have reported such efforts. For example, Toshiba reported that F and N co-implant at the halo implantation help could help to reduce the external resistance and improve NFET drive current. For pFET, Toshiba and IBM jointly announced a new Twisted Direct Silicon Bonding Technology to achieve higher hole mobility (Ref).
  • AMAT and TSMC reported a novel low-K spacer technology featuring CVD-SiBCN material with low dielectric constant of 5.2 and film stress of 430MPa to boost AC and DC CMOS performance.
  • The decade-old W contact technology is approaching its life limit. As the contact hole gets smaller, contact resistance is increasing, partly due to the contact barrier material. Various W replacements have been sought after. Among them Cu is the most desirable since wealth of knowledge on Cu technology has been built up over the last decade. This year, NEC reported a Direct Low-K/Cu Dual Damascene Contact Lines technology that can significantly improved the RO improved by approximately 7%.
  • Intel divulged more details on its Nehalem chip and 45nm high-k/metal-gate technology. Intel claimed that stress enhancement due to “gate last” increases the stress benefit of eSiGe.The amount of Ge in the eSiGe has also increased from 22% in 65nm tech to 30% in 45nm technology. In addition, Intel also employs trench contact in NMOS to compensate for the loss of tensile strain from the absence of Tensile stress layer. The trench contact also has an added benefit of lowering the contact resistance by >50%. Another notably piece of work by Intel is the Floating Body Cell (FBC) for cache memory. The FBC technology could potentially be introduced at the 16 nm node and further scaled to the 10 nm technology generation (Ref). All together, Intel contributed 5 papers to this year Symposium.

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Jun

24

Siltronic Samsung Wafer Official Opening in Singapore

Filed Under Semiconductor Industry, Video Gallery | 1 Comment

The Siltronic Samsung Wafer, a $1 billion joint venture between Samsung Electronics and Germany’s Siltronic, was officially opened last week by Singapore Prime Minister Lee Hsien Loong. This is one of the largest 300mm silicon wafers plant in the world. The plant, located at Tampines high tech park, will gear into high volume production in 2010 with a monthly output of 300,000 wafers. By then, it will provide more than 800 jobs, from engineering to clean room operators (Ref).

The opening of Siltronic Samsung Wafer is another major milestone for Singapore semiconductor industry which consists of 14 wafer fabrication plants including the world’s top three wafer foundry companies (TSMC, UMC and Chartered) , 19 chip test and assembly plants, and about 40 design centers. The Singapore Semiconductor Industry contributes about 10% global market share of semiconductor wafer foundry output. It is currently employing ~34,000 people and accounting almost 30 percent of the electronics and engineering section in Singapore. One of the biggest challenges for the Singapore Semiconductor Industry is to source for enough talents to support the ecosystem of this industry. This is not going to be easy as new emerging industries in Singapore, such as Solar industry and Renewable Energy Industry, are draining away talents from the Semiconductor Industry. In addition, semiconductor industry is considered a mature industry and young engineering graduates would prefer new emerging industries which offer more opportunities.

Below is a video clip on Singapore SEMICON 2008 held last month.

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