Jul

29

Explosive Growth for Thin Film Photovoltaic (TFPV) Market

Filed Under Related Industry, Video Gallery | 2 Comments

According to NanoMarkets newest report “Thin Film Photovoltaics Markets: 2008 and Beyond”, thin-film photovoltaic (TFPV) market will grow from almost $2.4 billion ($US) in revenues in 2008 to over $12 billion in 2013. By 2015, NanoMarkets expects that TFPV will have a market opportunity of over $22 billion (Ref). The explosive growth is unfathomable a few years ago when TFPV was just a tiny niche area of photovoltaic’s business and was associated with low-margin products such as calculators. However, the advances of TFPV technology and the perennial shortage of crystalline silicon have driven TFPV technology to become the mainstream for PV market. In addition, TFPV technology shows great potential for low-cost, low-weight and flexible solar cells.

The current TFPV technology is still largely based on amorphous silicon (a-Si) which is well understood. However, non-silicon TFPV technologies, such as Copper Indium Gallium Deselenide (CIGS), cadmium telluride (CdTe), and GaAs etc, are gaining traction and may soon replace a-Si TFPV technology. In particular, GICS seems to offer all the virtues of TFPV with energy conversion efficiencies comparable to conventional PV of about 20 percent. One interesting development of CIGS TFPV technology is the possibility of building a flexible PV panel, such as CIGS on foil technology (Ref). A recent report from Lux Research claimed that TPFV build on flexible surfaces will make up 28 percent of the solar market by 2012 (Ref).

Below is a video on the manufacturing of solar panel from Q Cells:

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Jul

23

SEMICON WEST: Double Patterning for 32nm and 22nm

Filed Under Equipment | 1 Comment

The biggest semiconductor trade show in North America, SEMICON WEST 2008 has concluded couple of days ago (15-17 July). One of impending issues facing the semiconductor industry is the lithography solutions for 32nm and 22nm. It is pretty obvious now that EUV lithography will not be deployed for 32nm, and most likely will not be ready for 22nm as well. On the other hand, the immersion lithography technology which has served the semiconductor industry pretty well for 45-40nm will face its own limitations for 32nm and beyond. To bridge the gap for 32nm and 22nm before EUV lithography comes on board, the semiconductor industry is now betting on double patterning lithographic technology coupled with 193nm immersion lithography. However, as AMD Fellow Harry Levinson aptly summarized the current challenges of DP technology as “double patterning doubles the troubles” (Ref).

There are a number of variants for double patterning technology, such as double-exposure; trench double-patterning; line double-patterning; litho-etch-litho-etch, spacer and others. Whatever the variants, the biggest concerns with double-patterning technology are cost and overlay, particularly the overlay between the two exposures. To mitigate the overlay constraints, AMAT has introduced the Self-Aligned Double Patterning (SADP) Scheme. Samsung Electronics and Hynix Semiconductor Corp have announced they would use SADP for their 3x generation NAND flash. The IM Flash also reported that it would employ something similar to SADP for the 34nm memory devices (Ref).

During the SEMICON WEST 2008, IMEC announced a new variant of the double patterning technology which significantly reduces the cost. The new process first exposes the resist with the first pattern, apply a chemical enhancement to freeze that pattern into the material, expose the second pattern, and then develop and etch the resist normally. The big advantage of this approach is that the wafer stays on the litho track for both exposures. It doesn’t have to go off to a separate etch track and then back onto the litho track. (Ref)

On the other note, ASML has rolled out a new generation of 193-nm immersion scanner for double-patterning applications, Twinscan XT:1950i during the SEMICON WEST. It has an overlay below 4-nm and throughput of 175 wafers an hour. The system uses a lens with the same 1.35 numerical aperture (NA) as its predecessor, however the resolution has improved from 40 nm to 38 nm, which effectively provides a 10% gain in wafer area available for chips (Ref). You can watch a videos ads from ASML of this system below.

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