Jul

23

SEMICON WEST: Double Patterning for 32nm and 22nm

Filed Under Equipment | 1 Comment

The biggest semiconductor trade show in North America, SEMICON WEST 2008 has concluded couple of days ago (15-17 July). One of impending issues facing the semiconductor industry is the lithography solutions for 32nm and 22nm. It is pretty obvious now that EUV lithography will not be deployed for 32nm, and most likely will not be ready for 22nm as well. On the other hand, the immersion lithography technology which has served the semiconductor industry pretty well for 45-40nm will face its own limitations for 32nm and beyond. To bridge the gap for 32nm and 22nm before EUV lithography comes on board, the semiconductor industry is now betting on double patterning lithographic technology coupled with 193nm immersion lithography. However, as AMD Fellow Harry Levinson aptly summarized the current challenges of DP technology as “double patterning doubles the troubles” (Ref).

There are a number of variants for double patterning technology, such as double-exposure; trench double-patterning; line double-patterning; litho-etch-litho-etch, spacer and others. Whatever the variants, the biggest concerns with double-patterning technology are cost and overlay, particularly the overlay between the two exposures. To mitigate the overlay constraints, AMAT has introduced the Self-Aligned Double Patterning (SADP) Scheme. Samsung Electronics and Hynix Semiconductor Corp have announced they would use SADP for their 3x generation NAND flash. The IM Flash also reported that it would employ something similar to SADP for the 34nm memory devices (Ref).

During the SEMICON WEST 2008, IMEC announced a new variant of the double patterning technology which significantly reduces the cost. The new process first exposes the resist with the first pattern, apply a chemical enhancement to freeze that pattern into the material, expose the second pattern, and then develop and etch the resist normally. The big advantage of this approach is that the wafer stays on the litho track for both exposures. It doesn’t have to go off to a separate etch track and then back onto the litho track. (Ref)

On the other note, ASML has rolled out a new generation of 193-nm immersion scanner for double-patterning applications, Twinscan XT:1950i during the SEMICON WEST. It has an overlay below 4-nm and throughput of 175 wafers an hour. The system uses a lens with the same 1.35 numerical aperture (NA) as its predecessor, however the resolution has improved from 40 nm to 38 nm, which effectively provides a 10% gain in wafer area available for chips (Ref). You can watch a videos ads from ASML of this system below.

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Apr

16

IBM Alliance Touts 32nm High-k/Metal-Gate Ready

Filed Under Process Technology, Video Gallery | Leave a Comment

IBM and its Fishkill alliance development partners, including Chartered Semiconductor, Freescale, Infineon, Samsung, STMicroelectronics and Toshiba announced two days ago that they have made a significant breakthrough in the high-k/metal-gate (HKMG) process that results in 35 percent performance improvements on their 32nm technology as compared to 45nm technology at the same operating voltage. The IBM alliance also claims that they are ready for early customer engagement to use the new 32nm HKMG process. (Ref).

In contrast to Intel HKMG process which employs a gate-last approach (also known as replacement gate process), IBM alliance is using a more conventional gate-first approach for HKMG process. While the gate-first approach is simpler, more scalable, and migrate-able (easier to port designs from previous generation) as compared to gate-last approach, IBM’s gate-first HKMG process development is apparently lagging far behind Intel’s gate-last HKMG process which has already been in mass production since 2H 2007. One underlying significance from the above IBM alliance joint statement is that the alliance is now ready to catch up with Intel and TSMC in 32nm process development. It also boosts the confidence of the alliance in future joint development. One of alliance member, Chartered Semiconductor has just extended the joint development collaboration with IBM to include 22-nanometer CMOS (Ref).

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