Apr

30

TSMC pushes for Foundry 2.0, OIP, 40nm, high-k and CPU

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The world largest contract chip maker, Taiwan Semiconductor Manufacturing Co. Ltd (TSMC), has made a series of high profile moves recently. During last week VLSI Week seminar, Chairman of TSMC, Morris Chang, unveiled a new business model for foundry, known as Open Innovation Platform (OIP) that aims to shorten clients’ time to market and reduce their development and manufacturing costs (Ref). You can watch Morris Chang’s speech in the video below. Some people also aptly coined the new OIP model “Foundry 2.0″ which signifies the second generation of fabless-foundry model. Based on the OIP or Foundry 2.0 model, foundry will offer vertically integrated services to customers, from designing (design tools and IP) and manufacturing (traditional foundry service) to testing and packaging. Hmmm…Does it mean that fabless can just handoff their design RTL to the foundry, and they will get packaged parts from the foundry rather than getting only wafers? Anyway, TSMC hopes that through the new platform, it can establish a more extensive and deeper technical cooperation with its customers.

Besides the ambitious OIP initiative, TSMC is also aggressively developing its own silicon-proven IPs, such as embedded flash, embedded DRAM and embedded CPU, as well as pushing the envelop on process technology. According to Ref, TSMC’s 40G process will be in risk production at the end of this year and become quite significant next year, while its 32LP process is expected to ready by the end of this year. TSMC also announces that its 32HP will offer high-k/metal-gate option.

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Mar

26

TSMC readies 40nm technology for production

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The world’s largest contract chipmaker has announced the readiness of its 40 nm manufacturing process technology for both a general purpose and low-power applications. TSMC plans to offer low-power 40nm technology for wireless and portable devices, and general-purpose 40nm technology for CPUs, GPUs, FPGA and other high-performance consumer devices. The company already has orders for such chips from customers. Production is expected to begin in the second quarter of 2008. (Ref).

TSMC claims that the its 40nm technology has the smallest footprint in the industry with 2.35× higher raw gate density and a SRAM cell size of 0.242 µm2. In addition, the 40nm technology offers significant saving in power as compared to its 45nm technology. The 40 nm process uses a combination of 193 nm immersion photolithography and ELK (Extreme Low-k) material. The 40G and LP processes will initially run in TSMCs Fab 12 and will be transferred to Fab 14 as demand ramps (Ref).

EDN Executive Editor Ron Wilson pointed out an interesting observation that the gap between TSMC 45nm and 40nm is surprisingly short, just 2Q difference (Ref). TSMC 45nm technology was ready in Sep 2007, and its 40nm technology is now ready in Mar 2008. Ron suggested that this probably was TSMC’s strategy to engage the fabless customers, such as Qualcomm and Altera, to 45nm as early as possible despite the 45nm might not be quite ready last year. The real production-ready process is actually the 40nm technology. The following video showed TSMC presentation to Altera on 45nm few months ago.

 

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